FIG. 1 diagramatically shows in perspective a known EPROM cell, i.e. an electrically programmable, read-only memory cell erasable by ultraviolet radiation. As shown in FIG. 1, a memory point is formed from a transistor having a source 4 and a drain 6 produced in a silicon monocrystalline semiconductor substrate 8. The source and drain have opposite conductivities to those of the substrate.
The transistor also comprises a gate insulant 10, generally of silicon oxide, on which are stacked a first gate 12 and a second gate 14, generally of phosphorus-doped polycrystalline silicon. These two gates are separated by a fine insulant film 16, which is generally of silicon oxide. The first gate 12 is a floating gate and the second gate 14 the control gate of the memory point.
This memory point is electrically insulated by means of a field oxide 18 produced by local, surface oxidation of the substrate from the other memory points, as well as the peripheral control circuits of said memory point.
The complete memory cell is covered with a thick insulating layer 22, generally of silicon oxide, in which are formed the electrical contact holes of the sources and drains such as 24. The electrical connections between the sources and drains of the different memory points and/or the different peripheral control circuits are provided by a conductive layer 26, which is generally of aluminum, which is deposited on the insulating layer 22 and appropriately etched.
The electrical connections between the control gates of the different memory points are defined at the same time as the control gates 14 and in the same polycrystalline silicon layer.
Attempts are increasingly being made to reduce the size of integrated circuits and in particular memories with a view to increasing their integration density. Unfortunately, in the presently known memories two factors limit the reduction in the dimensions of the memory cell.
The first factor is the overlap between the floating gate 12 and the field oxide 18. An overlap X1 of the floating gate 12 above the field oxide 18 and an overlap Y1 of the field oxide 18 with respect to the floating gate 12 are necessary due to the imprecision of superimposing of the different layers constituting the memory points and lithography masks necessary for the etching of the different layers. These overlaps are respectively in the direction X of the word lines (or gate connections) of the memory cell and in direction Y of the channels of the memory points, i.e. perpendicular to direction X.
The second factor is the need to provide insulating guards around the contact holes of the bit line, i.e. around the contact holes of the drains of the memory points. An insulating guard X2 is provided in direction X between the drain contact and the field oxide 18 and another insulating guard Y2 is provided in direction Y between the drain contact and gates 12, 14.
The reduction of the lithographic dimensions are not generally accompanied by a proportional improvement in the superimposing accuracies of the different levels, particularly lithographic masks, so that the limiting factors referred to hereinbefore will become increasingly more disadvantageous for increasing the integration density of memories.
Self-alignment or self-positioning processes avoiding the overlap between the floating gate and the field oxide and/or insulating guards around the contact holes consequently become necessary for future generations of memories.